Welcome to the official website of Shenzhen Yishan Memory Technology Co., Ltd
Service hotline 86-755-2391 2131
You are here:Home >> Product >> SAMSUNG Samsung

Product

Product

Contact us

Contact: Mr. Li / Miss King

Tel:+86-755- 
23912131

Fax: +86-755-82727420

QQ: 2058566930 

E-mail: 
yishanic001@gmail.com 

Zip code: 518000

Address: 
Room 1220, New Asia Guoli building, No. 18, Zhonghang Road, Huahang community, Futian District, Shenzhen

SAMSUNG Samsung

S3C4510B01-QE80

Model: S3C4510B01-QE80

Brand: SAMSUNG  


Type: original             quantity: 75330

Package: QFP208      batch number: 18+ROHS

Price: enquiry              sample: support         specification: contact customer service.

Description: 16/32-BIT RISC MICROCONTROLLER

  • RoHS:YES
    RoHS Version:2002/95/EC
    Description: 16/32-BIT RISC MICROCONTROLLER
    Taxonomy:Microcontrollers and Processors "Microcontrollers" Microcontrollers
    Supplier Cage Code:1542F

    Samsung Group is the largest multinational enterprise group in South Korea, and it is also the top 500 of the listed companies. SamSung group includes a large number of international subordinates. The SamSung group includes Samsung Electronics, Samsung, Samsung, and Samsung Life Insurance. The business involves electronic, financial, mechanical, chemical and other fields. Leading storage series FLASH/DRAM/SDRAM/DDR/EMMC and ARM.

    The ARM processor is the first low-cost RISC microprocessor designed by the British Acorn limited. The full name is Advanced RISC Machine. The ARM processor itself is a 32 bit design, but it is also equipped with a 16 bit instruction set, which generally saves 35% of the equivalent 32 bit code, but keeps all the advantages of the 32 bit system.
    The three characteristics of the ARM processor are: less power consumption, powerful functions, 16 bit /32 bit dual instruction set and many partners.
    1, small volume, low power consumption, low cost and high performance.
    2, support Thumb (16 bit) /ARM (32 bit) dual instruction set, which can be well compatible with 8 bit /16 bit devices.
    3, the number of registers is used, and the instruction execution speed is faster.
    4, most data operations are done in registers.
    5. The method of addressing is flexible and simple, and the execution efficiency is high.
    6. The length of the instruction is fixed.
    Architecture editing
    Architecture
    1 CISC (Complex Instruction Set Computer, complex instruction set computer)
    In the various instructions of the CISC instruction set, about 20% of the instructions will be used repeatedly, accounting for 80% of the whole program code. The remaining instructions are not used frequently, and account for only 20% of the programming.
    2 RISC (Reduced Instruction Set Computer, reduced instruction set computer)
    The RISC structure selects the simple instructions with the highest frequency to avoid complex instructions, reduce the length of the instruction, reduce the type of instruction format and addressing mode, and use the control logic, without or less use of microcode control.
    The RISC architecture should have the following characteristics:
    1, using fixed length instruction format, instruction reset, simple and basic addressing method has 2~3 kinds.
    2 use single cycle instruction to facilitate pipelined operation.
    3 a large number of registers are used, and the data processing instructions only operate on the registers. Only the loading / storage instructions can access the memory to improve the efficiency of the instruction execution.
    In addition, the ARM architecture has adopted some special technologies to minimize the chip area and reduce power consumption on the premise of ensuring high performance.
    4 all instructions can be executed according to the result before execution, thereby improving the efficiency of instruction execution.
    5 load / store instructions can be used to bulk transfer data to improve data transmission efficiency.
    6 logic processing and shift processing can be completed in a data processing instruction simultaneously.
    7 in order to improve operation efficiency, we use address automatic increase or decrease in cyclic processing.
    Register structure
    The ARM processor has 37 registers, which are divided into several groups (BANK). These registers include:
    The 131 general-purpose registers, including the program counter (PC pointer), are all 32 bit registers.
    The 26 status register is used to identify the working state of CPU and the running state of the program. They are all 32 bits and only use part of them.
    Instruction structure
    The ARM microprocessor supports two kinds of instruction sets in the new architecture: ARM instruction set and Thumb instruction set. Among them, the ARM instruction is 32 bit length, and the Thumb instruction is 16 bit length. The Thumb instruction set is a functional subset of the ARM instruction set, but compared with the equivalent ARM code, it can save more than 30% to 40% of the storage space and have all the advantages of the 32 bit code.
    Architecture expansion
    The current expansion of the ARM architecture includes:
    Thumb 16 bit instruction set to improve code density;
    The arithmetic operation instruction set of the DSP DSP application;
    Jazeller allows direct execution of Java bytecode.
    The solutions provided by the ARM processor series are:
    . an open platform for wireless, consumer electronics and image applications;
    Storage, automation, industrial and network application of embedded real-time system;
    Security applications of smart cards and SIM cards.
  • Please submit your basic information and we will reply you as soon as possible! 

    *

    *

    *

    *

Related products

CopyRight© 2017 Shenzhen Yishan Memory Technology Co., Ltd All Rights Reserved Web Design—Tiandixin