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Understanding DDR5 in five minutes

Time:2020-07-24 Views:484
Nowadays, double data rate (DDR) synchronous dynamic random access memory (SDRAM or directly called DRAM) technology has become a common memory in almost all mobile applications from high-performance enterprise data centers to power/area-focused mobile applications.
All this is due to the high-density characteristics of DDR, and its simple architecture using capacitors as storage elements has the characteristics of high performance, low latency, high access life and low power consumption.
Three DDR standards have been developed in the definition of JEDEC (Solid State Technology Association): standard DDR, mobile DDR, and graphics DDR to help designers meet memory requirements. JEDEC‘s current latest generation in the DDR category is DDR5. According to Wikipedia news, as of September 2019, the standards for such products are still waiting for JEDEC to determine and are expected to be released in 2020.
DDR5 will support higher data rates (up to 6400 Mb/s) with lower I/O voltage (1.1V) and higher density (based on 16Gb DRAM die) than DDR4. DDR5 DRAM and dual in-line memory modules (DIMMs) are expected to be on the market this year.
This article outlines several main functions of DDR5 DRAM, which designers can deploy in system-on-chip (SoC) types such as servers, cloud computing, networking, notebook computers, desktops, and consumer applications.

What is standard DDR?
Standard DDR DRAM with high density and high performance is available in various models and form factors, supporting data widths of 4 (x4) or 8 (x8) or 16 (x16) bits. End applications can use these memories as discrete DRAM or DIMMs.
DIMM is a printed circuit board (PCB) module with multiple DRAM chips that supports 64 or 72 bit data width. 72-bit DIMMs are called Error Correcting Code (ECC) DIMMs. In addition to 64-bit data, they also support 8-bit ECC.
Server, cloud and data center applications usually use 72 ECC DIMMs based on 4 DRAMs, which can support higher RAS (reliability, availability, maintainability) functions while obtaining higher density DIMMs. In addition, such ECC DIMMs can also shorten the downtime of such applications in the event of a memory failure.
In addition to higher performance, DDR5 also introduces a variety of RAS functions to maintain the stability of the channel after speed-up. These DDR5 channel stability features include: duty cycle adjuster (DCA), on-chip ECC, DRAM receive I/O equalization, cyclic redundancy check (CRC) of RD and WR data, and internal DQS delay monitoring. The following is a detailed description of these functions:
1. Duty cycle adjuster (DCA) to compensate for duty cycle distortion
The duty cycle adjuster allows the host to compensate for the duty cycle distortion on all DQS (data strobe)/DQ (data) pins by adjusting the internal duty cycle of the DRAM. Therefore, the DCA function consolidates the stability of reading data.
2. Enhanced on-chip ECC of RAS
DDR5 DRAM sets up an 8-bit ECC storage space for each 128-bit data, making the on-chip ECC have a powerful RAS function that can protect the memory array from single-bit errors.
3. DRAM obtains DQ equalization to increase margin
Like LPDDR5 DRAM, DDR5 DRAM also supports WR data equalization. This feature opens up a new situation for WR DQ on the DRAM side, not only can protect the channel from inter-symbol interference (ISI), increase the margin, but also achieve higher data rates.
4. Cyclic Redundancy Check (CRC) of RD/WR data
DDR4 only supports CRC for writing data, while DDR5 extends the scope of CRC to read data to provide additional protection and avoid channel errors.
5. Internal DQS delay monitoring
The internal DQS delay monitoring mechanism supports the host to adjust the DRAM delay to compensate for voltage and temperature changes. A host running at DDR5 speed can use this function to retrain the channel periodically to compensate for VT changes caused by delays in DRAM.
to sum up
In order to meet the requirements of target applications, DDR has become one of the necessary technical solutions when designers choose the best off-chip memory technology for their designs. From the earliest 400 Mbps DDR to today‘s 6400 Mbps DDR5, the data rate of each generation of DDR has doubled.
With the increase in the number of cores, DDR5 provides higher density (including dual-channel DIMM topology) to ensure channel efficiency and performance. These advantages are suitable for servers, cloud computing, networks, laptops, desktops, and consumer products. The applied SoC is the most important. No matter which DDR DRAM technology the designer chooses, a compatible interface IP solution must be deployed in the SoC to achieve the necessary connection with the DRAM.
Synopsys provides a silicon-proven DDR memory interface IP product portfolio, which can implement DDR5/4/3/2, LPDDR5/4/4X/3/2, and HBM/HBM2E DRAM and DIMM. The DesignWare® DDR IP complete solution also includes a controller, an integrated hard macro PHY in an advanced FinFET process, and verification IP.
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